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Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities
• Must have worked in at least 1 Full Chip tape outs.
• Must be hands-on technical expert.
• Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling)
• Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks)
• Experience in Low power and high-performance designs.
• Be able manage junior team members.
Should be able to comprehend architecture, architectural limitations from Physical Design perspective, schedule, and volume of the task and personnel requirement
Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3000+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.
Job ID: 104666149
Skills:
redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking
Skills:
routing, block level place and route, floor-planning, Power grid analysis, Extraction, Physical Synthesis, Netlist, full chip implementation, GDS flow, STA timing, flow-automation, Signal Integrity, clock tree optimization, formal verification, Dft, Timing Constraints, Regression, digital design automation, Timing Closure, CTS IO timing, RTL-to-GDSII, Antenna fixing
Skills:
PERL, Python, Tcl, Sta, CTS, Timing Convergence, ICC2, RTL2GDSII flow, Ir, Tempus, Block-level and Full-chip Floor-planning, primetime, Innovus, Synthesis, Physical Verification, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure
Skills:
DFT (Design for Testing), System Verilog, low power design, SOC design, Clock/Voltage Domain Crossing
Skills:
Dsp, C++, Soc, Route, Python, Fc, Tcl, power analysis, Physical Design, Floorplan, Innovus, formal verification
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