redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

routing, block level place and route, floor-planning, Power grid analysis, Extraction, Physical Synthesis, Netlist, full chip implementation, GDS flow, STA timing, flow-automation, Signal Integrity, clock tree optimization, formal verification, Dft, Timing Constraints, Regression, digital design automation, Timing Closure, CTS IO timing, RTL-to-GDSII, Antenna fixing

PERL, Python, Tcl, Sta, CTS, Timing Convergence, ICC2, RTL2GDSII flow, Ir, Tempus, Block-level and Full-chip Floor-planning, primetime, Innovus, Synthesis, Physical Verification, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure

DFT (Design for Testing), System Verilog, low power design, SOC design, Clock/Voltage Domain Crossing

Dsp, C++, Soc, Route, Python, Fc, Tcl, power analysis, Physical Design, Floorplan, Innovus, formal verification