Python, Tcl, floorplanning, Physical design flows, Clock CTS, Logical Equivalence, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

Routing, floorplanning, Sta, CTS, primetime, Fusion Compiler, ICC2, Innovus, PNR, Physical Design, Placement, Timing Closure, Sign-off

C, Perl, Tcl, C++, Routing, Clock Planning, Physical Verification, floorplanning, Timing Closure, Physical Design Implementation, Innovus, Calibre, primetime, Placement, ICC2, LEC, EDA Tools

Perl, Python, Tcl, Physical Design flow, Sta, primetime, Fusion Compiler, ICC2, Tempus, UPF, Innovus, low power design, MMMC concepts, Physical Verification, CPF

Tcl, Python, PERL, ECO Timing Closure, Synthesis, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Ir, Physical Verification, Innovus, CTS, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Seahawk, Place And Route, Timing Convergence, High Frequency Design Methodologies

Tcl, Routing, Perl, 28nm and lower technology nodes, Timing Constraints, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, Methodologies, CTS, Innovus, Sta, ICC2, Tk, Placement, Timing Closure, PT-PX, sub-micron technology, Netlist2GDSII Implementation

layout verification , Design For Testing (DFT), System on a Chip (SoC), Very Large Scale Integration (VLSI) design, Computer Engineering, System Verilog, ASIC Design, Electrical Engineering, Computer Science, Low power designs, Design rules

Physical Design, Synthesis, RTL2GDS, primetime, floorplanning, EDA Tools, Synopsys Fusion Compiler, Cadence Innovus, Tempus