Provide technical and managerial Leadership to a PD team for a SoC Chip development owning partitions and full-chip from synthesis to place and route through all sign-off including timing signoff, physical verification, EMIR signoff, and formal verification.
Influence tools, flows, and overall design methodology in design construction, signoff, and optimization.
Work closely with architecture/RTL/DFT/DV/Package development teams.
Be a technology expert in the area of Physical Design with in the team and business Unit.
Minimum Qualifications
10 to 15 years of experience in Physical Design.
Proven experience in implementing designs through synthesis, Floorplanning, place and route, extraction, timing, and physical verification.
Technically lead a team of PD engineers on the Physical Design activities of complex SoCs.
Strong understanding of constraints generation, timing optimization, and timing closure and STA.
Strong technical problem solving and debugging ability
Experience in EDA tools related to Place and route, Synthesis, Physical Verification , STA etc.
Proficient understanding of CTS and different clock building techniques
Experience with multi-clock, multi-power-domain design, UPF etc
Experience in IP integration (memories, IO s, embedded processors, hard macros, Analog IP)
Knowledge of Microelectronics concepts
Scripting skills in Python, Tcl, C etc
Ability to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvements
