Senior Layout Engineer
Senior Layout Engineer
smartsoc solutions pvt ltd- Posted 10 hours ago
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Job Description
- Position : Memory Layout Engineer
- Experience: 3 to 8 years
- Location : Bangalore
- Notice Period : 0- 30 days
- Role:
- Layout Design of SRAM/CAM/RF custom/compiler memories in TSMC A14/2FF/3FF technologies or Samsung SS8/SS2 technologies.
- Responsibilities:
- Develop key building blocks of memory architecture, such as Row Decoder, IO, and Control.
- Skilled in pitched layout concepts and floor planning for Placement, Power, and Global Routing.
- Knowledge of EM/IR requirements.
- Compiler-level integration and final verification of Compiler/Custom memories.
- Strong knowledge of CMOS fabrication processes, foundries, and challenges in the latest technology nodes.
- Skills & Qualifications:
- Proficient in industry-standard EDA tools such as Cadence Virtuoso and Mentor Graphics Calibre.
- Strong problem-solving, logical reasoning, and communication skills.
- Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes.
- Extensive experience with physical verification tools such as Calibre and ICV (DRC, LVS, ERC, Antenna, and Softcheck Errors).
- Proficiency in floor planning, hierarchy layout, and chip integration.
- Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.
- Strong knowledge of memory layout topology; experience with memory compilers is preferred.
Interested candidate please share the updated resume to [Confidential Information]
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Key Skills
Antenna Electro Migration
Mentor Graphics Calibre
DRC
RC requirements
ICV
About Company
Skills:
Cadence Virtuoso, Analog Mixed-Signal Custom Layout, IR verification, Mentor Graphics Calibre, DRC, Antenna, EM, LVS, Dfm
Skills:
PERL, Python, Tcl, Skill, AI tools, PPA, multi-patterning, DRC, LVS, cell layout optimization, Cadence Virtuoso
Skills:
Calibre, design-rule constraints, FinFET technology nodes, layout optimization, physical verification methodologies, custom layout design, DRC, Parasitic Extraction, LVS, SRAM memory layout, Cadence Virtuoso
Skills:
Pvs, Analog layout design, die-to-bump connectivity, package substrate interactions, PEX, R3D, analog layout matching techniques, EM, Ir, IC Layout design, LVS, CAD Tools, Floor Planning, Calibre, Xl, Esd, DRC, PowerFET, virtuoso, Packaging
Skills:
Analog Design Environment (ADE), matching , parasitic extraction (PEX), shielding , Synopsys IC Validator, analog layout techniques, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, guard rings, interdigitation, Cadence Pegasus, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, symmetry, parasitic optimization, DRC, common centroid, reliability rules