Cadence Virtuoso, Analog Mixed-Signal Custom Layout, IR verification, Mentor Graphics Calibre, DRC, Antenna, EM, LVS, Dfm

PERL, Python, Tcl, Skill, AI tools, PPA, multi-patterning, DRC, LVS, cell layout optimization, Cadence Virtuoso

Calibre, design-rule constraints, FinFET technology nodes, layout optimization, physical verification methodologies, custom layout design, DRC, Parasitic Extraction, LVS, SRAM memory layout, Cadence Virtuoso

Pvs, Analog layout design, die-to-bump connectivity, package substrate interactions, PEX, R3D, analog layout matching techniques, EM, Ir, IC Layout design, LVS, CAD Tools, Floor Planning, Calibre, Xl, Esd, DRC, PowerFET, virtuoso, Packaging

Analog Design Environment (ADE), matching , parasitic extraction (PEX), shielding , Synopsys IC Validator, analog layout techniques, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, guard rings, interdigitation, Cadence Pegasus, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, symmetry, parasitic optimization, DRC, common centroid, reliability rules

layout verification , automation, Mentor Graphic Calibre DRC, AI tools, Layout Design, skill coding, Cadence VLE