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Senior IP Design Engineer
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Senior IP Design Engineer
Nxp Semiconductors- Posted 4 hours ago
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Job Description
In this role, you will be responsible for developing high-quality, reusable IPs for SoC/subsystem integration and driving designs from concept through silicon. This position offers an opportunity to work on cutting-edge semiconductor technologies and collaborate with global cross-functional teams.
Key Responsibilities
Work with architecture teams and put up the micro-architecture based on the IP requirements
Develop RTL using Verilog/SystemVerilog/VHDL based on micro-architectural specifications
Translate system-level requirements into high-quality IP designs
Optimize designs for power, performance, and area
Perform design checks such as Lint, CDC, synthesis, and STA
Drive bug fixing and closure
Support design reviews and sign-off processes
Collaborate with verification teams on test plans and coverage closure
Required Skills
Strong experience in RTL design (Verilog/SystemVerilog/VHDL)
Solid understanding of SoC/IP design and integration
Hands-on experience with:Lint, CDC, synthesis, timing analysis
Experience in Low-power design techniques
Preferred Skills
Experience in full-cycle IP/SoC development
Exposure to formal verification or low-power flows
Experience with post-silicon validation and bring-up
More information about NXP in India...
Key Responsibilities
Work with architecture teams and put up the micro-architecture based on the IP requirements
Develop RTL using Verilog/SystemVerilog/VHDL based on micro-architectural specifications
Translate system-level requirements into high-quality IP designs
Optimize designs for power, performance, and area
Perform design checks such as Lint, CDC, synthesis, and STA
Drive bug fixing and closure
Support design reviews and sign-off processes
Collaborate with verification teams on test plans and coverage closure
Required Skills
Strong experience in RTL design (Verilog/SystemVerilog/VHDL)
Solid understanding of SoC/IP design and integration
Hands-on experience with:Lint, CDC, synthesis, timing analysis
Experience in Low-power design techniques
Preferred Skills
Experience in full-cycle IP/SoC development
Exposure to formal verification or low-power flows
Experience with post-silicon validation and bring-up
More information about NXP in India...
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Post-silicon validation
Bring-up
SoC IP design and integration
Low-power design techniques
About Company
Skills:
Verilog, Rtl Design, VHDL, LINT, Timing Analysis, Synthesis, systemverilog, cdc, Low-power design techniques
Skills:
Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug
Skills:
static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts