Verilog, Rtl Design, VHDL, LINT, Timing Analysis, Synthesis, systemverilog, cdc, Low-power design techniques

Verilog, random stimulus, VMM, assertion-based verification, Uvm, systemverilog, functional coverage, advanced verification methodologies

static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts