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Senior DFT Engineer
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Senior DFT Engineer
Praxis Hr SolutionsQuick Apply
- Posted a month ago
- Over 50 applicants have applied
Job Description
Job Summary
- The DFT Engineer will design, implement, and verify state-of-the-art test architectures for complex System-on-Chips (SoCs) and ASICs. You will be responsible for defining the test strategy, executing test insertion, generating high-coverage patterns, and collaborating with post-silicon teams to debug hardware
More Info
Key Skills
DFT Methodologies
Scan Design
ATE Programming
Design Debugging
DFT Architecture
About Company
Skills:
retargeting , boundary scan , DFT architecture, pattern generation validation, MBIST, EDT OCC integration, Boundary Scan JTAG, Scan Architecture, IJTAG, DFT implementation debug, scan implementation, Memory IP Test Simulations
Skills:
simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, leading DFT activities, IP integration, DFT specification definition, SoC cycles, silicon debug activities
Skills:
Python, Clp, Tcl, Perl, JTAG BSCAN, MBIST, LEC, SoC DFT Architecture, Logic and DRC analysis, P1500 implementation, ZERO delay and SDF based scan, ATPG DRC analysis, Memory BIST implementation, Hybrid-TK Compression, LPCT, Stuck at TDF, Scan Insertion, power analysis methodologies, Test coverage debug, JTAG simulations, Bridging Cell-aware iddq fault models, LBIST, iJTAG
Skills:
Debugging, Logic Design, Sta, On-chip scan compression, ATPG, Gate level simulation, Fault Simulation, Automation methods, Scan BIST, Fault Models
Skills:
ATPG (Automatic Test Pattern Generation), logic bist , test coverage , Memory BIST (MBIST), DFT architecture, Digital DFT, Scan compression, SoC MCU architecture, DFT protocols, Debug effort