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Senior DFT Engineer
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Senior DFT Engineer
Praxis Hr SolutionsQuick Apply
- Posted a month ago
- Over 50 applicants have applied
Job Description
Job Summary
- The DFT Engineer will design, implement, and verify state-of-the-art test architectures for complex System-on-Chips (SoCs) and ASICs. You will be responsible for defining the test strategy, executing test insertion, generating high-coverage patterns, and collaborating with post-silicon teams to debug hardware
More Info
Key Skills
DFT Methodologies
Scan Design
ATE Programming
Design Debugging
DFT Architecture
About Company
Skills:
Boundary Scan JTAG, MBIST, pattern generation validation, DFT architecture, scan implementation, Memory IP Test Simulations, IJTAG, retargeting activities, DFT implementation, EDT, OCC integration, boundary scan methodologies, debug and analysis
Skills:
simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities
Skills:
Clp, Perl, Python, Tcl, Scan Insertion, Hybrid-TK Compression, SoC DFT Architecture, ATPG DRC analysis, P1500 implementation, Memory BIST implementation, JTAG BSCAN, MBIST, LEC, Bridging Cell-aware iddq fault models, iJTAG, Stuck at TDF, Logic and DRC analysis, Test coverage debug, ZERO delay and SDF based scan, LPCT, JTAG simulations, power analysis methodologies, LBIST
Skills:
occ, Memory-BIST, DFT architecture scan Insertion compression at core level and SoC level, SSN architecture, timing and no-timing simulations, clock architecture, ATPG pattern generation coverage analysis
Skills:
Logic Design, Sta, On-chip scan compression, Fault Simulation, Automation methods, Fault Models, Tessent, Gate level simulation, ATPG, Scan BIST, Pattern generation, VLSI simulation tools