Senior DFT Engineer

DFT methodologies, PDL development, pattern validation, post-silicon pattern handoff, Siemens Tessent tools, gate-level DFT verification

Non-volatile Memory (Flash, Dft, MRAM, MBIST, ReRAM, Synopsys, iJTAG IEEE 1687, SoC MCU Architecture, TestMAX, Functional Safety, power management, JTAG IEEE 1149.1, ATPG, Scan Compression, Mentor, Tessent, Audio, Rf, Mixed-signal Design, LBIST, Ate, Digital Design Flows

simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities

DFT architecture, coverage analysis, Memory-BIST, ATPG pattern generation, compression at core level, Scan Insertion, SSN architecture, clock architecture, timing simulations, no-timing simulations, occ

Logic Design, On-chip scan compression, Scan BIST, Fault Simulation, ATPG