Senior Staff Engineer - DFT
Senior Staff Engineer - DFT
Infineon Technologies- Posted 11 hours ago
- Be among the first 10 applicants
Job Description
#WeAreIn to leverage synergies contributing to Infineon's product development. Are you in
Your role
Key responsibilities in your new role
Qualifications And Skills To Help You Succeed
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in
We are on a journey to create the best Infineon for everyone.
We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.
Our hiring decisions are based on skills and experience. Even if you don't meet every requirement, we encourage you to apply.
Please let your recruiter know if you need any accommodations during the interview process.
Learn more about our various contact channels and about Diversity & Inclusion at Infineon.
GOWRI SHENOY
https://www.linkedin.com/in/gowri-shenoy-33894217/
Your role
Key responsibilities in your new role
- Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip
- Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures
- Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification
- Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck at/TDF/Bridging/Cell-aware/iddq fault models
- Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations
- Hands on experience in analysis and debug of above-mentioned test domains
- Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out
Qualifications And Skills To Help You Succeed
- Bachelor's degree (B.E./B.Tech.) in Electrical/Electronics Engineering or Master's degree (M.E./M.Tech.) in VLSI Design or a related field
- 12+ years of experience in DFT implementation, verification, and post-silicon debug
- Strong understanding of the complete ASIC design flow
- Hands-on experience with LEC, CLP, and power analysis methodologies is highly desirable
- Proven expertise in delivering complex SoC designs, encompassing DFT specification development, implementation, verification, and post-silicon debug
- Self-driven professional with a passion for continuously improving DFT methodologies and design processes
- Excellent analytical and problem-solving abilities, with the capability to work independently, manage multiple priorities, and collaborate effectively within cross-functional teams
- Strong interpersonal and teamwork skills, with the ability to thrive in a diverse and dynamic work environment
- Proficiency in scripting languages such as Perl, Tcl, and Python is preferred
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in
We are on a journey to create the best Infineon for everyone.
We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.
Our hiring decisions are based on skills and experience. Even if you don't meet every requirement, we encourage you to apply.
Please let your recruiter know if you need any accommodations during the interview process.
Learn more about our various contact channels and about Diversity & Inclusion at Infineon.
GOWRI SHENOY
https://www.linkedin.com/in/gowri-shenoy-33894217/
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Hybrid-TK Compression
SoC DFT Architecture
ATPG DRC analysis
P1500 implementation
Memory BIST implementation
JTAG BSCAN
Bridging Cell-aware iddq fault models
iJTAG
Stuck at TDF
Logic and DRC analysis
Test coverage debug
ZERO delay and SDF based scan
LPCT
JTAG simulations
power analysis methodologies
LBIST
About Company
Skills:
occ, Memory-BIST, DFT architecture scan Insertion compression at core level and SoC level, SSN architecture, timing and no-timing simulations, clock architecture, ATPG pattern generation coverage analysis
Skills:
Pre-silicon DFT verification, Post-silicon validation, Yield improvement, BSCAN, Hierarchical multi-core test strategies, MBIST, Scripting and automation, Scan compression, GLS, Power-aware DFT, ATPG simulation, ATPG, Debug, DFT timing closure, LBIST, ATE test program development, Coverage closure, IJTAG, Silicon bring-up
Skills:
Vcs, Perl, Python, Tcl, ATPG Fault Models, DFT Debugging, Siemens Tessent, Synopsys TestMAX, End-to-end DFT implementation, RTL SoC Design Flow, Cadence Modus, STA Timing Closure, MBIST LBIST, DFT Sign-off Fault Coverage, JTAG Boundary Scan – IEEE 1149.1, Scan Insertion Compression