Senior DFT Engineer
Senior DFT Engineer
ALTEN Calsoft Labs- Posted 15 days ago
- Be among the first 10 applicants
Job Description
Senior DFT Engineer
Experience : 4–5 years
Location : Bangalore
Experience to join our Silicon Engineering team. In this role, you will lead end-to-end DFT strategies—including Scan compression, MBIST, IJTAG, and ATPG pattern generation—for high-performance, sub-10nm SoCs. Candidates must have expertise in top-tier EDA tools (Tessent, Synopsys, or Cadence) and a notice period of 0–30 days.
Ready to elevate your career Send your resume to [Confidential Information] today!
More Info
Key Skills
About Company
Skills:
Boundary Scan JTAG, MBIST, pattern generation validation, DFT architecture, scan implementation, Memory IP Test Simulations, IJTAG, retargeting activities, DFT implementation, EDT, OCC integration, boundary scan methodologies, debug and analysis
Skills:
Jtag, MBIST, FastScan, DFT architecture, Scan Insertion, ATPG, Synopsys TetraMax, EDT, Scan Compression, Stuck-at, At-speed, TestKompress, Mentor Tessent
Skills:
scan compression, BSCAN, Simulation, MBIST, DFT insertion, ATPG, LBIST, pattern generation, IJTAG
Skills:
Scan, HDLs, MBIST, DFT architecture definition, Tempus, ATPG flow implementation, scripting skills in Perl, Genus, tessent DFT, JTAG boundary scan, Cadence digital implementation tools
Skills:
test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, equivalence check DFT DRC rules, simulating test vectors, ATPG coverage analysis, Cadence Encounter Test, DFTMax, timing fixes corrective actions for timing violations, ASIC DFT