Senior DFT Engineer
Senior DFT Engineer
ALTEN Calsoft Labs5-7 Years
- Posted 6 hours ago
- Be among the first 10 applicants
Job Description
We're Hiring! Senior DFT Engineers at ACL Digital | Bangalore
Are you passionate about Design-for-Test (DFT) and looking for your next challenge ACL Digital is expanding our VLSI team, and we are looking for experienced DFT Engineers to join us in Bangalore.
Key Requirements:
- Experience: 5+ years of hands-on experience in DFT.
- Technical Expertise: Strong proficiency in DFT architecture, Scan Insertion, Scan Compression (EDT), ATPG (Stuck-at, At-speed), MBIST, and JTAG.
- Tool Exposure: Hands-on experience with tools such as Mentor Tessent (TestKompress/FastScan) or Synopsys (TetraMax).
- Problem Solving: Proven ability in coverage analysis, DFT DRC clean-up, and timing/zero-delay simulations.
- Availability: Looking for candidates with a notice period of 30–45 days.
Why Join Us
At ACL Digital, you'll work on cutting-edge semiconductor projects, collaborating with a high-performing team and engaging in complex end-to-end SoC designs.
How to Apply:
Interested candidates, please share your updated resume at [Confidential Information] or DM me directly
#Hiring #DFTEngineer #VLSIJobs #Semiconductor #DFT #BangaloreJobs #ACLDigital #JobOpening #VLSI
More Info
Key Skills
DFT architecture
Synopsys TetraMax
EDT
Scan Compression
Stuck-at
At-speed
Mentor Tessent
About Company
Skills:
Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan
Skills:
Python, Perl, Logic Design, Profiling Tools, Uvm, Post Silicon Testing, SV, Constrained random testing, Architecture Verification, DFT Engineering, Coverage metrics
Skills:
Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence
Skills:
scan compression, BSCAN, Simulation, MBIST, DFT insertion, ATPG, LBIST, pattern generation, IJTAG
Skills:
Scan, HDLs, MBIST, DFT architecture definition, Tempus, ATPG flow implementation, scripting skills in Perl, Genus, tessent DFT, JTAG boundary scan, Cadence digital implementation tools