Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows

Makefile, Octave, MATLAB, Digital Signal Processing, Scripting Languages, Perl, Python, functional code coverage analysis, UVM-based testbench infrastructure, HW emulation, FPGA prototyping, formal verification, functional cover point development, Power aware simulations, gate level simulations, APB protocol, IP and SoC level verification, assertion development

C, Perl, Python, System Verilog, formal verification tools, Microarchitecture, SOC integration, Uvm

arm architecture , C, Ethernet, Pcie, Usb, DDR, HBM, Uvm, SoC DV execution, assertion-based formal verification tools, TLMs in SystemC, hardware emulation support

System Verilog, Coverage models, DV methodology, Testbench design, Uvm

Jtag, System Verilog, Python, Pcie, Perl, UVM methodology, High speed USB, UltraSoC, RISC Debug Architectures, Design for Debug, Tessent Embedded Analytics

rtl verification , SystemVerilog PLI coding, Verilog simulations, Sram, AI-assisted tools, Timing Analysis, DRAM, UVM Test Bench