Senior Design Verification Engineer
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Take the lead in advanced design verification!
We're looking for a Senior Design Verification Engineer in Bangalore to work on:
Key Skills: System Verilog/UVM, protocol verification
Experience Required: 3+ Years
Join our team and help shape groundbreaking designs.
SmartSoC Solutions is emerging as a leader in providing engineering solutions worldwide. We offer end-to-end Semiconductor, Embedded, Automotive and System Design to design and build next-generation leadership products under one roof. And allowing clients to achieve both quick wins and long-term results.
Our goal is to be an extended arm of engineering product and IT companies and ensure good quality productization cost-effectively.
Job ID: 113017089
Skills:
Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers
Skills:
wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies
Skills:
Perl, Tcl, Python, Uvm, MIPI DSI, systemverilog, HDMI, DisplayPort
Skills:
Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip
Skills:
Computer Architecture, Verilog, Uvm, systemverilog, coverage-driven verification, advanced stimulus generation
