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Take the lead in advanced design verification!
We're looking for a Senior Design Verification Engineer in Bangalore to work on:
Key Skills: System Verilog/UVM, protocol verification
Experience Required: 3+ Years
Join our team and help shape groundbreaking designs.
SmartSoC Solutions is emerging as a leader in providing engineering solutions worldwide. We offer end-to-end Semiconductor, Embedded, Automotive and System Design to design and build next-generation leadership products under one roof. And allowing clients to achieve both quick wins and long-term results.
Our goal is to be an extended arm of engineering product and IT companies and ensure good quality productization cost-effectively.
Job ID: 113017089
Skills:
Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog
Skills:
Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB
Skills:
Mac, Pcie, Switches, Ethernet, FPGA verification, RDMA, NICs, SmartNICs, networking architectures, Uvm, systemverilog
Skills:
Unix, Makefile, Shell, Configuration Management, PERL, System Verilog, Python, Verification dashboarding tools, ARM CPU, PCI Express, Uvm, AMBA bus protocols, Ethernet bus protocols
Skills:
Verilog, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog
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