Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog

Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

Mac, Pcie, Switches, Ethernet, FPGA verification, RDMA, NICs, SmartNICs, networking architectures, Uvm, systemverilog

Verilog, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog

Vcs, Git, Pcie, Ethernet, System Verilog, low-power verification techniques, cdc, Uvm, UPF, C Language, Axi, level shifter implementation, AMBA, FIFOs, APB, Questa, RISC-V CPU subsystems, clock reset architectures, power management strategies, AHB

analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis

Scripting Languages, Sed, Awk, Perl, ARM processor based SoC architecture, ASIC design flow, ASIC verification methodologies, C Assertions coding, multi-core multi-layer APIs, functional coverage, SV-UVM, constraint random test generation, UVM assertion based coverage driven verification, ARM based SOC software framework

Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping