Senior Design Verification Engineer with strong expertise in PCIe Gen5/Gen6, SystemVerilog, and UVM to drive IP/SoC-level verification for highspeed interfaces and ensure firsttimeright silicon.
Exp-6+years
Location- Bengaluru, Hyderabad,Noida
Key responsibilities:
- Own verification strategy and test plan for PCIe Gen5/Gen6 controller/IP at block, subsystem, and SoC level.
- Architect, develop, and maintain UVMbased verification environments, agents, scoreboards, and coverage for PCIe and related highspeed interfaces.
- Develop constrainedrandom and directed tests in SystemVerilog/UVM to validate protocol features, LTSSM states, power management, error handling, and link training for Gen5/Gen6.
- Collaborate closely with RTL, architecture, and validation teams to refine specifications, review microarchitecture, and close functional and code coverage.
- Debug complex failures using simulation, waveforms, assertions, and protocol analyzers; drive rootcause and issue closure with crossfunctional teams.
- Integrate and use PCIe VIP, checkers, and protocol compliance suites; ensure adherence to PCIe Base specifications and ecosystem interoperability requirements.
- Contribute to verification methodology improvements, scripting/automation for regressions, and best practices for highspeed protocol verification.
- Mentor junior engineers on UVM, PCIe protocol concepts, and debug techniques as a technical goto person in the team.
Required skills and experience
- 6+ years of ASIC/SoC design verification experience with a strong focus on PCIe Gen5/Gen6 or other highspeed serial protocols.
- Solid handson expertise with SystemVerilog and UVM, including building reusable environments, sequences, agents, and coverage models.
- Strong understanding of PCIe protocol (layers, TLP/DLLP, LTSSM, flow control, error reporting, link training, and equalization), preferably Gen5/Gen6.
- Proven experience in constrainedrandom verification, functional/code/MC coverage, assertions (SVA), and coverage closure on complex IP/SoC designs.
- Proficiency with industrystandard simulators and regression environments; good scripting skills in Python/Perl/Shell for automation.
- Strong debug skills, problemsolving attitude, and ability to work in fastpaced, crosssite teams.
- Experience with related protocols like CXL, NVMe over PCIe, or AMBA/AXI interconnects.
- Exposure to postsilicon validation, FPGA/emulation, or labbased PCIe bringup and protocol analyzers.
- Knowledge of RTL design concepts, timing, and lowpower features for highspeed I/O subsystems.
Education:
- Bachelor's or Master's degree in Electronics, Electrical, Computer Engineering, or VLSI with a strong digital design and verification background.
About Us:
Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we're committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.
Website
https://www.siliconpatterns.com
