Job Summary
We are looking for an experienced Design Verification Engineer to join our VLSI team in Bangalore. The ideal candidate will have strong hands-on experience in SystemVerilog, UVM, and verification of complex SoC/IP designs.
Key Responsibilities
- Develop and execute verification plans for IP/SoC level designs
- Build and maintain SystemVerilog/UVM-based verification environments
- Create test scenarios, sequences, scoreboards, and functional coverage models
- Debug and analyze simulation failures; work closely with design engineers to resolve issues
- Perform coverage analysis (functional & code coverage) and drive closure
- Review design specifications and ensure verification completeness
- Support regression runs and automation
- Participate in design and verification reviews
Required Skills
- 5+ years of experience in Design Verification
- Strong proficiency in SystemVerilog and UVM
- Solid understanding of digital design concepts and RTL (Verilog/SystemVerilog)
- Experience with simulation tools (VCS, Questa, Xcelium, etc.)
- Knowledge of coverage-driven verification methodologies
- Hands-on experience with debugging complex verification issues
Good to Have
- Experience in SoC-level verification
- Knowledge of standard protocols (AMBA AXI/AHB/APB, PCIe, USB, etc.)
- Exposure to low-power verification and assertions (SVA)
- Scripting knowledge (Python, Perl, Shell)
Education
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related fields
Notice period- Immediate to 30 days or Serving notice period
