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Senior Design Verification Engineer
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L&T Technology is looking to hire for Design Verification Engineers.
Job Location : Bangalore
Detailed JD is below ::
Job Description DV Positions:
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Qualifications and Skills for DV Positions:
Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience
8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification
8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
Experience in development of UVM based verification environments from scratch
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs
Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Experience with revision control stems like Mercurial(Hg), Git or SVNJob Description DV Positions:
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Job ID: 153641329
Skills:
Usb, Mercurial, Svn, DDR, Git, Perl, Pcie, Ethernet, Python, Tcl, UVM methodology, AMBA, SoC level verification, UVM based verification environments, Design Verification infrastructure
Skills:
Perl, Vcs, Python, Tcl, Verdi, Questa, Uvm, systemverilog
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
Skills:
Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers
Skills:
C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling
