Senior Design Verification Engineer

Location: Hyderabad / Bangalore / Remote

Experience: 5-12 Years

Employment Type:

Full-timeAbout The Role: We are looking for a highly skilled Design Verification Engineer with strong expertise in PCIe Protocol (Gen5 / Gen6) to join our high-speed interface IP / SoC verification team.

You will be responsible for verifying cutting-edge PCIe controller and PHY designs for next-gen data center and AI/ML SoCs.

Key Responsibilities:

Own verification of PCIe Gen5/Gen6 Controller IP (Root Complex / End Point / Dual Mode).

Develop SystemVerilog / UVM based verification environment from scratch and maintain existing TB.

Understand PCIe architecture and verify features like:Transaction Layer, Data Link Layer, Physical LayerFLIT Mode (Gen6), PAM4 Signaling, FEC, L0p, L1 PM SubstatesFlow Control, VC, QoS, Ordering, Completion HandlingLTSSM, Link Training, Equalization, Lane MarginingPower Management, SR-IOV, ATS, PASID, DOE, IDE (Security)PCIe Error Injection and Error Handling (AER, ECRC, Poisoned TLPs)Develop test-plans, coverage-plans, assertions (SVA) and functional coverage for Gen5/Gen6 features.Run regressions, debug failures with designers and drive to closure - 100% code & functional coverage.Work closely with Design, Architecture, and Firmware teams.Expertise in PIPE Interface verification (PIFP, 64b/128b/256b).Experience with Protocol Analyzers, LeCroy / Keysight Exercisers is a plus.

If You Are Intrested Or Any Known Candidates Are There ,Please Share Me Resumes to Below Mentioned Mail ID: [Confidential Information]