Usb, Mercurial, Svn, DDR, Git, Perl, Pcie, Ethernet, Python, Tcl, UVM methodology, AMBA, SoC level verification, UVM based verification environments, Design Verification infrastructure

Perl, Vcs, Python, Tcl, Verdi, Questa, Uvm, systemverilog

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

Verilog, Tcl, Python, Perl, Uvm, VHDL, systemverilog

Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip

Spi, I2c, Gpio, Uart, Pcie, DDR, UVM methodology, I3C, QSPI, CXL, systemverilog, HBM