Senior Design Verification Engineer

We are looking for an experienced SoC Verification Engineer with 8+ years of hands-on experience and strong team-leading capabilities to join our growing team.

- Person should have 8 - 12 years of ASIC verification experience

- Must have hands on experience of technically leading a team of 3-8 engineers for 2+ years

- Should be able to come up with test bench architecture for IP/SOC projects

- Expertise in System Verilog and UVM testbench development

- Strong scripting skills (Python, Perl, Shell, etc.)

- Excellent hands-on experience with IP/SOC verification including waveform debugging using IUS, VCS, Questa and Verdi

- Knowledge on UVM based testbench development at-least 4 to 6 projects

-Knowledge of Test plan development, test case development, functional and code coverage closure

-Experience of working in a CPU (C/C++) based Verification environment is a huge plus

- Experience of working NOC based SOC is a huge plus

- Knowledge of GLS or low power verification is a plus

- Excellent communication skills and demonstrate the desire to take on diverse challenges

- Proactively & independently drive assigned & Team's tasks to completion with full ownership

- Protocol knowledge of any one or more protocols is a huge plus (AMBA AXI/AHB/CHI, DDR, ARM CoreSight, PCIe, CXL, Ethernet, HBM, USB, etc.)