Senior Design Verification Engineer
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This job is no longer accepting applications
Experience:4+ years
Notice Period:0 to 30days
Location:Bangalore
Job Description.
1.Must Have: SoC or IP
2.Experience Languages : System Verilog (must)
3.Methodologies: OVM/UVM/VMM
4.Protocols:DDR/USB/Ethernet/PCIE/Video/HDMI/MIPI/DSI/CSI
5.Processor/ARM Based SoC Verification experience
6.Strong Analytical skills desirable if having worked.
Job ID: 151583041
Skills:
Pcie, Perl, Python, Tcl, protocol-level debugging, simulation and debug tools, verification methodology, UCIe, Uvm, FDI, systemverilog, coverage closure, CXL, RDI, SVA
Skills:
Perl, Verilog, Python, Uvm, SVA, systemverilog
Skills:
bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog
Skills:
Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers
