Senior Design Verification Engineer
Senior Design Verification Engineer
Mirafra Technologies4-6 Years
This job is no longer accepting applications
Job Description
Experience:4+ years
Notice Period:0 to 30days
Location:Bangalore
Job Description.
1.Must Have: SoC or IP
2.Experience Languages : System Verilog (must)
3.Methodologies: OVM/UVM/VMM
4.Protocols:DDR/USB/Ethernet/PCIE/Video/HDMI/MIPI/DSI/CSI
5.Processor/ARM Based SoC Verification experience
6.Strong Analytical skills desirable if having worked.
More Info
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Key Skills
About Company
Skills:
Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage
Skills:
C, Pcie, Perl, Python, Tcl, ONFI, LPDDR, NAND
Skills:
Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA
Skills:
Emulation, Code coverage and coverage closure, Post-silicon validation, ASIC SoC Design Verification, PCIe protocol verification, SoC IP-level testbench development and integration, PCIe Verification IP, Functional coverage, SystemVerilog UVM, Assertions, formal verification
Skills:
wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies