Senior Design Engineer
Senior Design Engineer
Altera- Posted 3 hours ago
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Job Description
Job Details
Job Description:
Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We are driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance.
We are seeking a talented Logic Design Engineer to develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs.
Key Responsibilities
Regular
Shift
Shift 1 (India)
Primary Location:
Regus, Madhapur
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Job Description:
Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We are driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance.
We are seeking a talented Logic Design Engineer to develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs.
Key Responsibilities
- Participate in design development tasks throughout the IP development flow.
- Develops the logic design, register transfer level (RTL) coding, and simulation for an IP.
- Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
- Applies various strategies, tools, and methods to write RTL and optimize the logic to quality the design to meet the IP release requirement.
- Involve in design example creation, simulation example creation, IP integration and release process.
- Involve in IP design example brings up on hardware, hardware verification and failure debugging.
- 8+ years experience with bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
- Experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis
- Experience in programming with C/C++/Perl/Python/TCL/Unix Shell script
- Experience in FPGA design and programming is a plus.
- Experience in RTL validation is a plus.
- Ability to work with different teams, good communication and problem-solving skills.
Regular
Shift
Shift 1 (India)
Primary Location:
Regus, Madhapur
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Synopsys simulators
RTL validation
About Company
Skills:
C, Vcs, DDR, Pcie, Verilog, Scripting Languages, Python, Nvme, Perl, Ethernet, Tcl, PCIe Lecroy, Lab equipment, RTL simulation tools, Viavi Exerciser Analyzer, HBM, RTL Coding, LPDDR, Modelsim, Makefiles, IP SOC design methodologies, systemverilog, FPGAs, Axi, AMBA, UNIX Shells, CXL, APB protocol, AHB
Skills:
Python, UVM methodology, Standard cell layout automation, Optimization mathematics, Timing power and memory architectures, Cadence and Synopsys toolchains, systemverilog, device physics, AI ML techniques, CMOS fundamentals, Core machine learning algorithms
Skills:
Vcs, DDR, Pcie, Verilog, Scripting Languages, Python, Nvme, Perl, Ethernet, Tcl, C++, PCIe Lecroy, Lab equipment, RTL simulation tools, HBM, RTL Coding, LPDDR, Modelsim, Makefiles, IP SOC design methodologies, systemverilog, FPGAs, Axi, AMBA, UNIX Shells, CXL, APB protocol, AHB, Viavi Exerciser, Analyzer
Skills:
power optimization , Python, Tcl, Physical Verification, Routing Signal Integrity, Low Power Design Techniques, IC Validator ICV, floorplanning, Placement Optimization, Physical Signoff, LVS, Power Planning, Calibre, Physical Design, CTS Clock Architecture, STA Timing Closure, ERC, DRC, ECO Methodologies, MCMM Flows
Skills:
static timing analysis, routing, Innovus, LVS, Parasitic Extraction, Fusion Compiler, DRC, Placement, floorplanning, Clock Tree Synthesis, ICC2