C, Vcs, DDR, Pcie, Verilog, Scripting Languages, Python, Nvme, Perl, Ethernet, Tcl, PCIe Lecroy, Lab equipment, RTL simulation tools, Viavi Exerciser Analyzer, HBM, RTL Coding, LPDDR, Modelsim, Makefiles, IP SOC design methodologies, systemverilog, FPGAs, Axi, AMBA, UNIX Shells, CXL, APB protocol, AHB

Python, UVM methodology, Standard cell layout automation, Optimization mathematics, Timing power and memory architectures, Cadence and Synopsys toolchains, systemverilog, device physics, AI ML techniques, CMOS fundamentals, Core machine learning algorithms

Vcs, DDR, Pcie, Verilog, Scripting Languages, Python, Nvme, Perl, Ethernet, Tcl, C++, PCIe Lecroy, Lab equipment, RTL simulation tools, HBM, RTL Coding, LPDDR, Modelsim, Makefiles, IP SOC design methodologies, systemverilog, FPGAs, Axi, AMBA, UNIX Shells, CXL, APB protocol, AHB, Viavi Exerciser, Analyzer

power optimization , Python, Tcl, Physical Verification, Routing Signal Integrity, Low Power Design Techniques, IC Validator ICV, floorplanning, Placement Optimization, Physical Signoff, LVS, Power Planning, Calibre, Physical Design, CTS Clock Architecture, STA Timing Closure, ERC, DRC, ECO Methodologies, MCMM Flows

static timing analysis, routing, Innovus, LVS, Parasitic Extraction, Fusion Compiler, DRC, Placement, floorplanning, Clock Tree Synthesis, ICC2

Vcs, System Verilog, Xcelium, Verdi, DVE, Questa, Uvm, SVA assertions

Debugging Expertise, SoC Verification, Uvm, Verification Planning, C DPI Development, Scripting and Automation, systemverilog, Hardware-Software Integration, Coverage-Driven Verification

Place and Route processes, Top-level physical implementation, Synthesis for high-speed designs, Unix/Linux environment