Senior Analog Layout Engineer

Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company that delivers end-to-end chip solutions to global customers. The organization combines deep expertise across the semiconductor value chain to help clients build next-generation products with high performance, quality, and accelerated time-to-market. Its engineering team covers the full design spectrum, including Analog Circuit Design, RTL Design, Design Verification, Custom Layout, Physical Design, and Embedded Design, across process technologies from mature nodes like 65nm and 40nm to advanced nodes such as 7nm, 5nm, 3nm, and beyond. SiMaxTech emphasizes continuous learning, innovation, and execution excellence, offering holistic and scalable services throughout the full chip development lifecycle. With a customer-centric approach, the company aims to be the preferred global partner for semiconductor design, known for reliable, high-quality, and scalable solutions.

Role Description The Senior Analog Layout Engineer will be responsible for designing and implementing analog and mixed-signal layouts, ensuring compliance with foundry design rules and achieving optimal performance, area, and reliability. Day-to-day responsibilities include translating circuit schematics into optimized layout structures, performing floorplanning, matching-critical layout, parasitic-aware design, and collaborating closely with analog circuit designers to validate design intent. The role involves running layout versus schematic (LVS), design rule check (DRC), and other physical verification flows, resolving violations, and supporting tape-out activities. The engineer will also contribute to layout methodology improvements, documentation, and mentoring less-experienced team members. This is a full-time, on-site role based in Bengaluru.

Experience: 4+ Years

Location: Bangalore

Notice Period: Immediate to 30 Days

Qualifications

• Strong expertise in Layout Design and Custom Layout for analog and mixed-signal blocks.
• Solid understanding of Circuit Design, Analog design fundamentals, and Analog Circuits behavior.
• Hands-on experience with Physical Verification, including DRC, LVS, and reliability checks.
• Proficiency with industry-standard EDA tools for layout (e.g., Cadence Virtuoso, Synopsys, Mentor) and verification.
• Experience working across advanced and mature technology nodes, preferably from 65nm to 7nm or below.
• Ability to collaborate effectively with cross-functional design teams and communicate clearly in technical discussions.
• Strong problem-solving skills, attention to detail, and ability to manage multiple design tasks and deadlines.
• Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related field, with several years of relevant analog layout experience.