shielding , PEX, FinFET, matching symmetry, LVS, custom analog layout, layout optimization, ERC, post-layout simulation, DRC, parasitics performance, common-centroid interdigitation, Cadence Virtuoso

Analog Design Environment (ADE), matching , parasitic extraction (PEX), shielding , Synopsys IC Validator, analog layout techniques, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, guard rings, interdigitation, Cadence Pegasus, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, symmetry, parasitic optimization, DRC, common centroid, reliability rules

Pvs, BGA, Analog layout design, PEX, R3D, EM, Ir, IC Layout design, Calibre, Xl, virtuoso, Wire bond, DRC LVS Packaging, Flip chip, Package substrate design, BCD nodes