Search Jobs
Search by job, company or skills
Search by job, company or skills
Job ID: 147221689
Skills:
python, perl, static timing analysis, Bash, Tcl, verification flow, digital design fundamentals, Uvm, scripting automation, systemverilog, Rtl Design, VHDL, synthesis tools
Skills:
Cache, Verilog, LINT, Synthesis, cdc, memory compression, timing power analysis, digital logic design principles, systemverilog, logic synthesis techniques, Dft, RTL design concepts, RDC, fabric coherence, ASIC design methodologies, DRAM, low-power design techniques
Skills:
Ethernet architectures, Source synchronous design implementation, Ethernet 802.3 protocol, RTL Coding, SerDes fundamentals
Skills:
static timing analysis, Verilog, Synthesis, Design Reviews, SoC debug architecture, SoC integration, DFT concepts, formal verification tools, ARM coresight components, systemverilog, Rtl Design, Simulators, formal verification, constraints timing analysis, Optimization Techniques, Verification, APB protocol
Skills:
FPGA-SoC interfacing, Python Perl, Peripheral interfaces SPI I2C UART DDR4, Xilinx FPGA design and prototyping, AMBA protocols AXI AHB APB, Protocol analyzers SPI CAN Ethernet, Hardware debugging tools Oscilloscope Logic Analyzer, Micro-architecture definition and logic design, Implementation of DSP algorithms on FPGA Radar EW systems, RTL Design using Verilog VHDL, Constraints development linting CDC analysis, Simulation and verification methodologies, FPGA synthesis implementation and timing closure, High-speed interfaces PCIe Ethernet JESD204B C
We don’t charge any money for job offers
