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Bengaluru, India

Skills:

pythonperlstatic timing analysisBashTclverification flowdigital design fundamentalsUvmscripting automationsystemverilogRtl DesignVHDLsynthesis tools

Early Applicant
Bengaluru, India

Skills:

CacheVerilogLINTSynthesiscdcmemory compressiontiming power analysisdigital logic design principlessystemveriloglogic synthesis techniquesDftRTL design conceptsRDCfabric coherenceASIC design methodologiesDRAMlow-power design techniques

Early Applicant
Bengaluru, India

Skills:

Ethernet architecturesSource synchronous design implementationEthernet 802.3 protocolRTL CodingSerDes fundamentals

Early Applicant
Bengaluru, India

Skills:

static timing analysisVerilogSynthesisDesign ReviewsSoC debug architectureSoC integrationDFT conceptsformal verification toolsARM coresight componentssystemverilogRtl DesignSimulatorsformal verificationconstraints timing analysisOptimization TechniquesVerificationAPB protocol

Early Applicant
Bengaluru, India

Skills:

Logic DesignRtl DesignDebug skillsSynthesisFront-end design tools and methodologiesMicro-architectureStatic-timing closureCustom SoC ASIC productsGate-level simulationsBlock-level function verificationformal verification

Early Applicant
Bengaluru, India

Skills:

GitVerilogSystem VerilogRtl Designmicroarchitecture developmentcdcinterconnect logicFIFOsclock reset architectureslow-power design techniquesSDC and UPF constraint writing

Early Applicant
Bengaluru, India

Skills:

FPGA-SoC interfacingPython PerlPeripheral interfaces SPI I2C UART DDR4Xilinx FPGA design and prototypingAMBA protocols AXI AHB APBProtocol analyzers SPI CAN EthernetHardware debugging tools Oscilloscope Logic AnalyzerMicro-architecture definition and logic designImplementation of DSP algorithms on FPGA Radar EW systemsRTL Design using Verilog VHDLConstraints development linting CDC analysisSimulation and verification methodologiesFPGA synthesis implementation and timing closureHigh-speed interfaces PCIe Ethernet JESD204B C

Early Applicant
Bengaluru, India

Skills:

NocGpuPerlVerilogPerformance ModelingPythonTclSiemens flowshigh-bandwidth memory systemsCadencesystemverilogarchitecture explorationRtl DesignAxiNPUAPBEDA ToolsSynopsysAHB

Early Applicant
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