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RTL Design
Location: Bangalore
Experience- 4+ years
Must have
Educational Qualification: BE/ME or BTech /MTech
Preferred
Job ID: 148988743
Skills:
cache coherency , rtl development , Verilog, System Verilog, VHDL, design verification strategy, memory consistency, micro-architecture, Functional Verification
Skills:
rtl development , Verilog, System Verilog, spyglass, VHDL, CDC Spyglass, System Verilog Assertion, Linting
Skills:
Perl, Verilog, Python, Tcl, microarchitecture development, Synthesis, cdc, systemverilog, Rtl Design, RDC, EDA Tools, LINT, low-power methodologies, STA concepts
Skills:
MATLAB, Verilog, Python, PSK, BCH, RF Systems, LDPC, SDR Architectures, ADC DAC architectures, DSP Algorithms, FPGA Development, VHDL, Vivado, DVB-S2, JESD204B C, DVB-S2X, Xilinx, QPSK, Rtl Design
Skills:
ASIC RTL Design, systemverilog, Micro-Architecture, Clock/Reset Design, Low-Power Design, UPF
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