ASIC RTL Design Engineer

Proxelera Private Limited

7-12 Years

Bengaluru

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Job Description

Responsibilities:

Own RTL design for SoC-level blocks or large subsystems from specification to silicon bring-up.
Define and implement micro-architecture; write high-quality, synthesizable RTL in SystemVerilog/Verilog.
Collaborate with physical design teams on synthesis, timing closure, power and area optimization, DFT hooks, and ECOs.
Drive block/subsystem integration and ensure seamless bring-up.
Work closely with verification teams to define test plans, assertions (SVA), and coverage goals.
Support silicon validation, post-silicon debug, and drive closure of design bugs.
Apply low-power design techniques (UPF, retention, isolation) and adhere to clock/reset design best practices.
Work on standard bus protocols such as AXI, ACE, AHB, and APB for interconnects, memory subsystems, and I/O integration.
Deliver production ASIC tapeouts, owning critical blocks like interconnects, coherency, memory subsystems, high-speed I/O, security, or power-management islands.
Enhance design productivity using scripting languages such as Tcl and Python to automate RTL development tasks.

More Info

Job Type:

Permanent Job

Industry:

Semiconductor

Role:

Hardware Design Engineer

Function:

Employment Type:

Full time

About Company

Proxelera Private Limited

Proxelera is your premier outsourced product development partner (OPD), specializing in Semiconductors, Systems, and Bespoke Hardware. Proxelera combines process rigour with advanced technical expertise to deliver transformative solutions while fostering industry-academia collaboration and VLSI talent development.

Job ID: 133332077

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Last Updated: 09-06-2026 00:04:34 PM

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