cache coherency , rtl development , Verilog, System Verilog, VHDL, design verification strategy, memory consistency, micro-architecture, Functional Verification

rtl development , Verilog, System Verilog, spyglass, VHDL, CDC Spyglass, System Verilog Assertion, Linting

Perl, Verilog, Python, Tcl, microarchitecture development, Synthesis, cdc, systemverilog, Rtl Design, RDC, EDA Tools, LINT, low-power methodologies, STA concepts

MATLAB, Verilog, Python, PSK, BCH, RF Systems, LDPC, SDR Architectures, ADC DAC architectures, DSP Algorithms, FPGA Development, VHDL, Vivado, DVB-S2, JESD204B C, DVB-S2X, Xilinx, QPSK, Rtl Design

ASIC RTL Design, systemverilog, Micro-Architecture, Clock/Reset Design, Low-Power Design, UPF

Verilog, Cache, Soc Architecture, fabric coherence, memory compression, systemverilog, logic synthesis techniques, FPGA and emulation platforms, digital logic design principles, Synthesis, DRAM, FPGA design verification, assertion-based formal verification, RTL design concepts, Dft, low-power design techniques, power analysis

Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications

static timing analysis, Synthesis, Front End SoC quality efficiency guardrails, SoC integration, low-power design architecture verification, 6G Radio Solutions, clock domain crossing, Soft Radio SOCs, Rtl Design, 5G, Optimization Techniques, formal equivalence checking, low-power design

Area, PPA Performance, Micro-architecture, Timing, LPDDR6, Rtl Design, JEDEC specifications, DDR Controller