Verilog, Ethernet Protocols, LINT, Rtl Design, spyglass, Synthesis, cdc, RDC, PPA optimization, systemverilog

Automation Frameworks, Sta, LINT, Memory operation, Synchronous design concepts, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, spyglass, Synthesis, device physics, CDC methodologies

Debugging, Tcl, Verilog, Python, Perl, Mentor, Synopsys, Timing Analysis, systemverilog, EDA Tools, low-power design concepts, cdc, Rtl Design, Cadence, digital IP development, AHB, Synthesis, APB, Axi, RDC, AMBA protocols

Python Scripting, Git, PrimeTime or equivalent tools, Modern SOC tools including Spyglass, Version control systems such as Perforce, ASIC design flow, Low power digital design and analysis, Digital Design, C embedded experience, VCS simulation, Cadence Conformal, ICManage, ASIC design in sub-20nm technology nodes, Questa CDC, RTL design in Verilog, Circuit timing STA

arm architecture , PERL, Python, Tcl, cdc, LINT, SoC level design integration, Digital Design, timing exceptions, writing UPF, Timing Constraints, design reuse, automation using scripting techniques, RTL Coding, designing with multiple power domains, CHI protocol

conformal lec , Tcl, Verilog, Python, Perl, VSI, LINT, UPF, IPXACT, Phys GPIOs, RTL Coding, SoC IP level Integration, IORING, Design Partitioning, Formality, VC spyglass