RTL Design Engineer
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Hi Folks
ACL Digital is Hiring!
Experience: 4 - 5+ Years
Location: Bangalore / Hyderabad
Looking: Immediate to 20 days
Hiring | RTL Design Engineer
Strong experience in RTL Design using Verilog/System Verilog
Exposure to complex SoC/ASIC design and integration
Hands-on with synthesis, Lint, CDC preferred
Share resume at [Confidential Information]
#RTLEngineer #ACLdigital #VLSIJobs #ASICDesign #Verilog #SystemVerilog
#SoC
Thanks,
K Himabindu
Job ID: 144751053
Skills:
Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications
Skills:
Verilog, low power microarchitecture techniques, logic design principles, VHDL, waveform debugging tools, high performance techniques, Simulators, microprocessor architecture
Skills:
Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog
Skills:
cache coherency , Verilog, Microarchitecture, Rtl Design, Digital Design, ip development
Skills:
Soc Architecture, Physical design interaction, SoC integration, Formal verification techniques and tools, Verilog RTL development, UPF and low-power methodologies
