RTL Design Engineer
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Job Description
Hi Folks
ACL Digital is Hiring!
Experience: 4 - 5+ Years
Location: Bangalore / Hyderabad
Looking: Immediate to 20 days
Hiring | RTL Design Engineer
Strong experience in RTL Design using Verilog/System Verilog
Exposure to complex SoC/ASIC design and integration
Hands-on with synthesis, Lint, CDC preferred
Share resume at [Confidential Information]
#RTLEngineer #ACLdigital #VLSIJobs #ASICDesign #Verilog #SystemVerilog
#SoC
Thanks,
K Himabindu
More Info
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About Company
Skills:
Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer
Skills:
Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows
Skills:
FPGA Design, Perl, Verilog, Python, systemverilog, Synthesis Checks, Digital Design, Custom IP Development
Skills:
C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator
Skills:
Verilog, Fpga, VHDL, systemverilog, ASIC Design, Synthesis Tools, Timing Analysis, Verification Methodologies, Physical Design, low power design