Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows

FPGA Design, Perl, Verilog, Python, systemverilog, Synthesis Checks, Digital Design, Custom IP Development

C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator

Verilog, Fpga, VHDL, systemverilog, ASIC Design, Synthesis Tools, Timing Analysis, Verification Methodologies, Physical Design, low power design

Clp, Pcie, Qc Tools, IPXACT, cdc, Vlsi, LINT, FIFO, UPF, AMBA, arbitration techniques, SDC, RDC, RTL Coding, VCLP

VLSI FIFO arbitration techniques, static QCs viz LINT CDC RDC CLP VCLP, design and integration for various in-house vendor IPs subsystems and SoC, RTL Coding, QC tools flows and IPXACT, constraints like SDC UPF

rtl development , static timing analysis, Verilog, Digital Signal Processing, LINT, Synthesis, Debug, LEC, Simulation, Matlab modeling, FPGA prototyping

Clp, Pcie, Qc Tools, IPXACT, cdc, Vlsi, LINT, FIFO, UPF, AMBA, arbitration techniques, SDC, RDC, RTL Coding, VCLP