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Cadence IP Tensilica group is a leading provider of configurable embedded processor technology, with a growing presence in the Automotive Safety market. As a member of the Functional Safety Design Verification Team for Xtensa processors you will be responsible for development and verification of hardware and software safety mechanisms. You will implement simulation or emulation test benches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target safety and product verification goals. You will also assist with fault simulation and analyzing coverage information. You will work closely with the RTL, EDA, and Functional Safety teams. You will develop and deliver functional safety work products, including documentation needed for product safety certification.
Required Skills and Experience:
Cadence is a health technology company helping the nation’s most patient-centric health systems deliver more consistent, proactive healthcare every day. Cadence’s remote patient intervention solution couples powerful new technology with clinical excellence, providing its patients a precise and personal level of care all outside of the four walls of the hospital.At Cadence, we aim to exceed the expectations of our patients, clinicians, and partners every day. Our team values trust and autonomy, and we empower one another to make decisions, solve problems and build something better. We give clear, candid feedback with the utmost honesty and encouragement. If you’re interested in joining us, explore opportunities at www.cadence.care.
Job ID: 104691689
Skills:
Pvs, Makefile, Tcl, Python, Perl, hierarchical physical design strategies, EM-IR, ASIC design flow, Physical Verification, deep sub-micron technology issues, Physical Design, Innovus, Quantus, Tempus, Voltus, formal verification, Timing Closure, Tk, Cadence implementation tools, Genus
Skills:
C++, Verilog, Systemc, Python, Qos, Matplotlib, Pandas, Uvm, SV, spec, TLM, STREAM
Skills:
Spi, Pcie, Usb, Dac, Uart, Ethernet, ADC, power-aware simulations, gate-level simulations, PLLs, Mentor Graphics Questa, Cadence Xcelium, low-power verification using UPF, Uvm, security IPs, I²C, functional coverage, eSPI, constrained-random verification methodologies, systemverilog, SoC-level verification, crypto engines, Synopsys VCS, Flash Memory, Analog IPs, ARM-based microcontrollers
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