Pvs, Makefile, Tcl, Python, Perl, hierarchical physical design strategies, EM-IR, ASIC design flow, Physical Verification, deep sub-micron technology issues, Physical Design, Innovus, Quantus, Tempus, Voltus, formal verification, Timing Closure, Tk, Cadence implementation tools, Genus

C++, Verilog, Systemc, Python, Qos, Matplotlib, Pandas, Uvm, SV, spec, TLM, STREAM

Spi, Pcie, Usb, Dac, Uart, Ethernet, ADC, power-aware simulations, gate-level simulations, PLLs, Mentor Graphics Questa, Cadence Xcelium, low-power verification using UPF, Uvm, security IPs, I²C, functional coverage, eSPI, constrained-random verification methodologies, systemverilog, SoC-level verification, crypto engines, Synopsys VCS, Flash Memory, Analog IPs, ARM-based microcontrollers