Principal Design Engineer

Key Responsibilities

Digital Architecture & Design

• Define and develop digital architecture with focus on Power, Performance, and Area (PPA) trade-offs
• Translate architecture into micro-architecture and RTL implementation
• Refine features and requirements throughout the design lifecycle

RTL Design & Implementation

• Develop high-quality RTL for SerDes IP components
• Ensure correctness, performance, and scalability of digital designs
• Work on behavioral modeling for IP development

Low Power & Optimization

• Implement low-power design techniques including power islands, isolation, and state retention
• Work on power management strategies for complex IP systems
• Optimize designs for performance, area, and power efficiency

Synthesis & Timing Analysis

• Perform synthesis and timing closure activities
• Generate and validate SDC constraints
• Ensure timing and functional correctness across design flows

Verification & Debugging Support

• Collaborate with verification teams to define coverage points and test strategies
• Debug verification issues including SVA failures and corner cases
• Support stimulus creation and validation scenarios

Cross-Functional Collaboration

• Work closely with analog, mixed-signal, verification, and project management teams
• Coordinate across global engineering teams
• Support IP development lifecycle from architecture to delivery

Automation & Tooling

• Develop scripting solutions for design automation workflows
• Use and enhance tool flows for IP quality control