C, System Verilog, Python, low power design, Synthesis constraint generation, Digital architecture, Debugging verification test cases, Embedded uC Designs, Synthesis, Dft, power management, Scripting of design automation, Behavioral coding, Digital RTL, Timing Analysis

Product Quality, Root Cause Analysis, semiconductor quality improvement, Failure Analysis, IC design, Analog Design, Digital Design

static timing analysis, EDA tools for synthesis, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC