Principal Design Engineer

constraint analysis , Perl, Verilog, System Verilog, Tcl, Sta, Synthesis, Simulation, synthesis logic equivalence, timing constraints generation, STA tools and flow, design for test, IP ASIC timing constraints generation, Dft, formal verification, backend related methodology and tools, LINT, Timing Closure, Design Methodologies, functional coverage, timing closure of various test modes

Phase Interpolator, SERDES, Driver, Circuit Simulation, Physical Verification, Deserializer, Layout, CMOS design, Bias and Bandgap Voltage Regulators, Receiver, jitter and signal equalization techniques, High Speed Clock Distribution, Serializer, Low jitter PLL

Low-power Implementation, Physical Verification, Physical Design, Timing Closure, Floor Planning, EDA Tools, Power Grid Design, Power Planning

static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

Digital Logic Design, Embedded Firmware, Scripting Languages, Verilog, System Verilog, Jtag, IEEE1500, MBIST, UPF, Memory dump, Scan dump, DFT architecture, Power management verification, Micro-processor debug, C Language, Hardware