Pcie, Verilog, Ethernet, Synthesis, cdc, UALink, Simulation, timing considerations, UCIe, systemverilog, LINT, CXL

hierarchical layout techniques, 3nm technology, Mentor Graphics Calibre, custom layout design, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices

conformal lec , Clp, Perl, Python, Tcl, Fusion Compiler, Formality, LEC, MCMM methodologies, UPF, Cadence Genus, Synthesis, Synopsys Design Compiler, RTL-to-GDS, CPF, Low Power Verification

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

bandgaps, CMOS image sensors, Simulation, noise analysis, Pll, Dft, bias op-amps, transistor level circuit design, top chip integration, Verification, LDOs, tapeout, AI tools, ADC architectures, analog mixed signal design, SERDES, switched-cap circuits, Timing Analysis, Silicon Bring up, feedback and compensation techniques, TCAD, high-speed TX, CMOS pixel design techniques, transistor capacitor matching, mixed-signal chip design