Debugging, Regression Testing, Test Planning, Design Verification, IP Verification, systemverilog, Uvm, Testbench Development, Verification Architecture, Simulation, Coverage Closure

Cadence tool experience, jitter and signal equalization techniques, Phase Interpolator, layout and physical verification, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES