Job Overview
As a Principal Analog Design Engineer at Tevega Semi, you will be a lead architect and designer for our next-generation Voltage Regulator (VR) IP portfolio. Your primary mission will be to design breakthrough analog architectures for Integrated VR (IVR), VR Chiplets, and MBVR (Multi-Bridge Voltage Regulators). You will translate system-level power requirements into transistor-level implementations that push the boundaries of efficiency, transient response, and power density.
Location: Bangalore, India
Experience: 12-15+ years
Key Responsibilities
- VR Architecture & Design: Lead the design and development of high-efficiency switching regulators and linear regulators (LDOs) for IVR and MBVR applications.
- Chiplet-Based Power Systems: Architect analog blocks optimized for VR Chiplets, focusing on high-speed inter-chiplet communication and distributed power delivery interfaces.
- Transistor-Level Implementation: Design critical analog building blocks including high-speed comparators, precision bandgap references, error amplifiers, gate drivers, and current sensing circuits.
- System-Level Modeling: Conduct high-level behavioral modeling for power converters to establish KPIs and validate control loop stability before detailed circuit implementation.
- Advanced Simulation: Perform rigorous SPICE-level simulations (Spectre, HSPICE) across PVT corners, including Monte Carlo and EMIR analysis, to ensure 2026-standard reliability and yield.
- Layout Oversight: Guide custom layout engineers on critical floorplanning, matching, and parasitic minimization to ensure post-extraction performance aligns with silicon targets.
- Silicon Validation: Lead post-silicon bring-up and characterization of VR IPs, correlating lab results with design simulations to drive root-cause analysis for any deviations.
Required Skills & Qualifications
- Education: BE/BTech/ME/MTech/PhD in Electrical/Electronics Engineering.
- Experience: 1215+ years of hands-on experience in Analog/Mixed-Signal IC Design.
Core Competency VR Design:
- Proven track record in designing multiple switching converters (Buck, Boost, Multi-phase).
- Deep expertise in Integrated VR and Multi-Bridge (MBVR) topologies.
- Experience with Chiplet-to-Chiplet power delivery and advanced packaging constraints.
Technical Proficiency:
- Mastery of Cadence Virtuoso, Spectre, and layout parasitic extraction (LPE) flows.
- Strong understanding of control loop theory, stability analysis (Bode plots, phase margin), and compensation techniques.
- Expertise in advanced FinFET process nodes (5nm and below) and their impact on analog design (matching, noise, and reliability).
Leadership: Ability to mentor junior designers and drive technical decision-making across cross-functional (Digital, Package, and System) teams.
Please reach out to [Confidential Information]
