Principal Engineer, Analog Design Engineering

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Flow automation, LINT methodology, RDC verification, ECO methodologies, RTL integration, CDC verification

regulators , Verilog, Matlab, IC design CAD tools, RF and Analog Design, Mixed signal circuits, TX, Bandgap bias circuits, RX, Spice, ADCs, Silicon Germanium SiGe BiCMOS, Spectre, Pll, DACs, HSIM, Filters, Bipolar Complementary Metal Oxide Semiconductor technology

scoreboard , Verilog, System Verilog, Verification Plan, UVM Environment, Test Benches, AMBA protocols, Uvm, Assertions, Functional coverage coding, DDR protocol knowledge, Axi, RTL debugging, Code Coverage analysis, AHB

Unix, Dsp, Perl, Linux, Verilog, Ethernet Protocols, MATLAB, Python, System Verilog, formal verification, Uvm