Physical Verification Engineer

Job Title: SoC – Physical Verification Engineer

About Semifive

Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea's semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end design, SEMIFIVE has become the fastest growing silicon design company that offers the most comprehensive design solutions. SEMIFIVE's core business is its innovative SoC Platform that enables low-cost and high-efficiency SoC design, and also provides full turnkey silicon design services for global customers.

As the cost of developing an SoC and the demand for customized silicon continue to grow rapidly, SEMIFIVE's SoC Platform plays a critical role in turning innovative ideas into silicon. SEMIFIVE works closely with global technology leaders and is rapidly emerging as The New Global Hub of Custom Silicon.

Semifive India Design Centre, headquartered in Bangalore, is a rapidly growing capability centre responsible for delivering complex, multi-node SoC programs for global customers across the US, Europe, and Asia. The India team owns RTL-to-GDS execution, including physical implementation, timing, power, and signoff for turnkey silicon programs.

Job Summary

We are seeking a highly skilled Physical Verification Engineer to work on physical verification sign-off activities for complex SoC designs across advanced technology nodes. The ideal candidate will be responsible for executing and closing DRC, LVS, ERC, Antenna, and PERC sign-off checks while working closely with the Physical Design team to enable high-quality and timely tape-outs.

Key Responsibilities

Physical Verification Sign-off

• Perform Physical Verification (PV) sign-off for complex SoC designs across advanced technology nodes.
• Execute and analyze sign-off checks including.
• Design Rule Check (DRC)
• Layout Versus Schematic (LVS)
• Electrical Rule Check (ERC)
• Antenna Checks
• PERC (Programmable Electrical Rule Check)
• Debug and resolve physical verification violations to achieve sign-off quality
• Collaborate with foundry documentation and sign-off methodologies to ensure design compliance.

Physical Design Collaboration

• Work closely with Physical Design, Layout, and Sign-off teams to resolve PV issues.
• Support design iterations and Engineering Change Orders (ECOs) required for PV closure.
• Ensure timely delivery of clean layouts for successful tape-outs.

Tool & Flow Development

• Support and enhance Physical Verification methodologies and sign-off flows.
• Develop and maintain Tcl scripts to automate PV execution, debugging, and reporting.
• Improve verification efficiency through automation and process enhancements.

Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering, or a related field.
• 1-5 years of hands-on experience in ASIC Physical Verification.
• Strong understanding of:
• VLSI Physical Design flow
• Physical Verification methodologies
• Semiconductor manufacturing rules and sign-off requirements
• Hands-on experience with industry-standard Physical Verification tools.

Preferred Skills

• Experience with PV sign-off checks (Samsung Foundry experience preferred)
• Strong experience in debugging and closure of: DRC, LVS, ERC, Antenna, PERC violations
• Experience with advanced technology nodes.
• Hands-on experience with:Synopsys ICC2 / Fusion Compiler
• Siemens Calibre
• Strong Tcl scripting skills.

Why Join Us

At Semifive, Physical Verification Engineers play a critical role in delivering first-time-right silicon. Unlike traditional semiconductor companies where verification ownership is often limited, Semifive provides engineers with end-to-end exposure across the RTL-to-GDSII flow and opportunities to work on cutting-edge SoC designs.You will collaborate with world-class engineering teams across global locations, contribute to advanced technology node implementations, and help build robust physical verification methodologies in a rapidly growing custom silicon organization.