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• Lead full-chip physical verification and drive DRC/LVS signoff for complex SoC designs
• Develop custom design-specific checks and advanced verification methodologies
• Perform multi-patterning verification and optimization for advanced technology nodes
• Implement advanced fill strategies to meet density requirements while minimizing design impact
• Interface with foundry to resolve design rule clarifications and obtain waiver approvals
• Mentor verification engineers on debugging techniques and verification best practices
• Develop verification automation and flow improvements to enhance productivity
• Conduct verification correlation studies and drive signoff quality improvements
Bachelor Of Technology (B.Tech/B.E)
Job ID: 151127115
Skills:
Perl scripting, Python, Tcl, bumps, physical verification tools, innovus, IP integration, padrings, semiconductor device physics, fusion compiler, translator characteristics, ASIC physical design flows
Skills:
Scripts, sign-off processes, physical verification checks, ERC, physical verification methodologies, EDA Tools, DRC, automation flows, LVS, ASIC physical verification methodologies
Skills:
Tcl Scripting, Siemens Calibre, Physical Verification, Fusion Compiler, Antenna Checks, Synopsys ICC2
Skills:
DRC, Synopsys, Dfm, Antenna, LVS, Physical Verification, Calibre, Innovus, Mentor, ASIC Design, EDA Tools, RDL generation, PERC, ICC2, PnR tools, ERC, PV methodology, IO Bump planning
Skills:
Samsung foundries, Dfm, Antenna, Arm CPU designs, LVS, DRC, Physical Verification, TSMC, advanced technology nodes, PERC
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