Physical Design Engineer
Physical Design Engineer
Sevya Multimedia- Posted 21 days ago
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Job Description
SoC Physical Design Engineers
We need experienced engineers to work on the Physical Design & Implementation of SoCs in cutting edge technology and with complex functionality.
Skills:
3+ years of relevant experience in Block/SoC level Physical Design.
Experience in Block/SoC Physical Design in the following topics:
- PnR tools like ICC2/Innovus with regards to physical/timing convergence
- 14nm / 10nm / 7nm / 5nm process nodes
- Tapeout sign-off experience is a must using industry standard tools.
- Cadence Encounter/Synopsys ICC2 tool set
- SDC, STA and Equivalence checking
- Flow automation exposure will be an added advantage.
Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.
Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills
Traits:
- Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
- Solutions orientation; Quality driven; Execution minded
More Info
Key Skills
Synopsys ICC2 tool set
PnR tools like ICC2 Innovus
SKILL Shell
Python Script
About Company
Skills:
power optimization , Eda, Tcl Scripting, Python, power analysis, Sta, Agentic AI methodologies, DVFS, LEC, AI-driven optimization, Place And Route, UPF, Physical Verification, Timing Power closure, Asic Physical Design, Physical Verification, full chip and block level floor-planning, Eco, multi-Vt power domains, RTL to GDS Flow, CPF, LLM-assisted debugging, autonomous agents
Skills:
cadence encounter , Unix Linux, 14nm 10nm 7nm 5nm process nodes, SDC STA and Equivalence checking, Synopsys ICC2 tool set, PnR tools like ICC2 Innovus, Flow automation exposure, SKILL Shell, Tapeout sign-off experience, Python Script
Skills:
PERL, Python, Tcl, Cerebrus, Sta, Synthesis, physical verification tools, Cadence Innovus, Place and Route workflows, Synopsys Fusion Compiler