power optimization , Eda, Tcl Scripting, Python, power analysis, Sta, Agentic AI methodologies, DVFS, LEC, AI-driven optimization, Place And Route, UPF, Physical Verification, Timing Power closure, Asic Physical Design, Physical Verification, full chip and block level floor-planning, Eco, multi-Vt power domains, RTL to GDS Flow, CPF, LLM-assisted debugging, autonomous agents

cadence encounter , Unix Linux, 14nm 10nm 7nm 5nm process nodes, SDC STA and Equivalence checking, Synopsys ICC2 tool set, PnR tools like ICC2 Innovus, Flow automation exposure, SKILL Shell, Tapeout sign-off experience, Python Script

PERL, Python, Tcl, Cerebrus, Sta, Synthesis, physical verification tools, Cadence Innovus, Place and Route workflows, Synopsys Fusion Compiler