Physical Design Engineer

General Summary:

As a global technology leader, Qualcomm is committed to pushing the boundaries of innovation. We are seeking a Senior Hardware Engineer specializing in Static Timing Analysis (STA) to join our world-class team. This role focuses on timing convergence for complex SoCs, IP blocks, and advanced technology nodes. The ideal candidate will have deep technical expertise in STA, strong problem-solving skills, and the ability to collaborate across design, physical implementation, and tool development teams.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field and 6+ years of relevant experience
• OR
• Master's degree and 5+ years of experience
• OR
• PhD and 4+ years of experience in Hardware Engineering or related fields

Required Experience and Skills:

• 6+ years of hands-on experience in Static Timing Analysis (STA) for large ASIC/SoC designs
• Strong foundation in STA concepts including:
• Setup/Hold time analysis, Clock Skew, Latch Transparency
• Multi-cycle and zero-cycle path handling
• AOCV/POCV (Advanced/Parametric On-Chip Variation)
• Crosstalk, Noise Analysis, and Signal Integrity
• Hands-on experience with industry STA tools:
• Synopsys PrimeTime, Cadence Tempus
• Expertise in timing constraint management (SDC), including:
• Multi-voltage domains
• Multi-mode timing closure
• Domain crossings and feedthrough handling
• Familiar with full ASIC back-end design flows (RTL to GDS):
• Tools: ICC2, Innovus, PT, Tempus
• Experience in SPICE simulations (Hspice/FineSim), Monte Carlo runs, and silicon-to-SPICE correlation
• Proficiency in scripting languages such as:
• TCL, Perl, Python, Awk
• Strong collaboration and communication skills; experience working in cross-functional teams

Preferred Qualifications:

• Knowledge of Qualcomm Hexagon DSP IPs and their timing behavior
• Exposure to device physics and process technology enablement
• Familiarity with digital design flow and EDA automation
• Experience in timing methodology development and automation within STA/PD flows
• Previous experience in timing convergence for chip-level and hard macro-level designs

Key Responsibilities:

• Own and drive timing convergence for advanced SoC and IP designs across PVT (Process, Voltage, Temperature) corners
• Perform STA signoff using industry-standard tools and methodologies
• Develop, maintain, and optimize timing analysis flows and scripts
• Work with physical design teams to define and validate constraints, analyze violations, and recommend fixes
• Support cross-functional teams in constraint development, clock tree synthesis, and timing closure
• Correlate SPICE simulations with STA results to ensure timing accuracy and model validity
• Lead timing reviews, debug issues, and document findings and methodologies
• Contribute to tool evaluations, timing methodology enhancements, and internal flow automation

Level of Responsibility:

• Works independently and takes ownership of key deliverables
• Provides technical leadership and mentoring to junior engineers
• Influences project direction and STA methodology
• Communicates complex technical issues effectively to stakeholders