Physical Design Engineer
- Posted 22 days ago
- Over 100 applicants have applied
Job Description
Skills/Experience:
- Hands-on experience in complex SOC/sub-systems implementation using Innovus & Fusion Compiler.
- Proficient in top-down floorplan and Power Grid methodologies.
- Experience in signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff.
- Successful track records of taping out complex IPs & SoCs at 16/10/7/5 nm Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus.
- Automation and programming-minded, coding experience in Tcl/Tk/Perl.
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About Company
Skills:
Python, Tcl, Sta, DRC Closure, Advanced technology nodes, Post-Route Optimization, PnR Physical Design, PnR tool knobs recipes for PPA optimization, CTS Routing, Custom Clock Tree methodologies, H-Tree, Layer via optimization, Placement density and congestion challenges, Current-density analysis, floorplanning, CTS implementation, Power Planning, spine, Clock metrics optimization, ECO Implementation, Adaptive PDN, PG-Grid PDN optimization, High-frequency designs, Multi-point CTS
Skills:
Scripting, EDA Tool Proficiency, Cross-Functional Collaboration, Risk Issue Management, Team Leadership Mentorship, SerDes IP Integration, Architecture Methodology, Technical Ownership Project Planning, RTL-to-GDSII Execution, Advanced Technology Nodes, Stakeholder Vendor Alignment, Timing PPA Closure, SoC-Level Physical Design
Skills:
Ecos, Perl, Tcl, Python Scripting, Sta, CTS, Cadence Innovus, routing optimization, congestion optimization, SDC, MMMC, advanced technology nodes, full-chip physical implementation, constraint development, floorplanning, PPA improvements, Timing Analysis, setup hold closure, SI crosstalk, Timing Closure, complex SoC designs, Placement, Power Planning
Skills:
Tcl Scripting, Shell scripting, Python, Routing, Perl, Sta, Signoff, CTS, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Signal Integrity, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2
Skills:
Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog