Python, Tcl, Sta, DRC Closure, Advanced technology nodes, Post-Route Optimization, PnR Physical Design, PnR tool knobs recipes for PPA optimization, CTS Routing, Custom Clock Tree methodologies, H-Tree, Layer via optimization, Placement density and congestion challenges, Current-density analysis, floorplanning, CTS implementation, Power Planning, spine, Clock metrics optimization, ECO Implementation, Adaptive PDN, PG-Grid PDN optimization, High-frequency designs, Multi-point CTS

Scripting, EDA Tool Proficiency, Cross-Functional Collaboration, Risk Issue Management, Team Leadership Mentorship, SerDes IP Integration, Architecture Methodology, Technical Ownership Project Planning, RTL-to-GDSII Execution, Advanced Technology Nodes, Stakeholder Vendor Alignment, Timing PPA Closure, SoC-Level Physical Design

Ecos, Perl, Tcl, Python Scripting, Sta, CTS, Cadence Innovus, routing optimization, congestion optimization, SDC, MMMC, advanced technology nodes, full-chip physical implementation, constraint development, floorplanning, PPA improvements, Timing Analysis, setup hold closure, SI crosstalk, Timing Closure, complex SoC designs, Placement, Power Planning

Tcl Scripting, Shell scripting, Python, Routing, Perl, Sta, Signoff, CTS, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Signal Integrity, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2

Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog

Unix, Clp, Perl, Linux, Integration, Scripting, Tcl, floorplanning, PDN knowledge, LEC, PNR, STA flows, Optimization, Placement, ASIC Design, Verification, Validation