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Job Summary
As a member of the India Field Organization for the Digital and Signoff Group, you will partner closely with our top semiconductor customers to drive and build unique and innovative methodologies to implement cutting-edge designs. This involves working closely with the customers to understand their key challenges, develop efficient methodologies, help them leverage the latest tool capabilities, and guide them to achieve their design goals. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest designs that customers are working on, and have the ability to influence at all levels, both internally and externally.
This role also provides a front-row opportunity to participate in the evolution of key technology solutions to the most pressing design problems. In this role, you will have the opportunity to work with product teams to influence product direction with your timely feedback and observations.
In addition to wielding technical influence, your unique understanding of the customer and their key careabouts will have a deep impact on the business strategy. You will collaborate closely with the sales teams to help drive account strategy and campaigns.
This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other's success, and are passionate about technologyand innovation.
Job Responsibilities
Qualifications
Experience and Technical Skills required
Job ID: 149080425
Skills:
Debugging, Logic Design, Sta, Circuit Design, Physical Verification, PNR, Physical Design, EDA Tools, Optimization, Rtl Design
Skills:
Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation
Skills:
redhawk , Perl, Python, Tcl, EMIR sign-off flows, Voltus, electromigration analysis, Totem, chip-package co-simulation, EMIR sign-off methodology, chip-package co-design, PDN planning, PDN architecture planning
Skills:
static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, low-power design techniques, Place And Route, Clock Tree Synthesis
Skills:
PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure
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